A network processor generally controls the flow of packets between a physical transmission medium, such as a physical layer portion of, e.g., an asynchronous transfer mode (ATM) network or synchronous optical network (SONET), and a switch fabric in a router or other type of packet switch. Such routers and switches generally include multiple network processors, e.g., arranged in the form of an array of line or port cards with one or more of the processors associated with each of the cards.
Dynamic random access memories (DRAMs) are a preferred storage technology for use in conjunction with such network processors, in that DRAMs can provide a large storage capacity at limited power consumption. Also, DRAMs are inexpensive compared to other types of storage, such as static random access memories (SRAMs).
DRAMs within or otherwise associated with a network processor are typically arranged in the form of multiple memory banks. Consecutive read or write accesses to an address or addresses within a given one of the banks will require waiting a random cycle time Trc for completion of a required access pre-charge process. However, consecutive accesses to even the same address within different banks do not experience this Trc wait time, which is also referred to herein as the bank conflict penalty.
SRAMs avoid the bank conflict penalty altogether. That is, any address in the memory can be accessed in a fixed time without incurring the Trc wait time associated with DRAMs. However, in addition to being more expensive, their storage capacity is typically an order of magnitude lower, and their power consumption is typically two orders of magnitude higher, relative to comparably-sized DRAMs.
U.S. Pat. No. 6,944,731, issued Sep. 13, 2005 in the name of inventors G. A. Bouchard et al. and entitled “Dynamic Random Access Memory System with Bank Conflict Avoidance Feature,” commonly assigned herewith and incorporated by reference herein, discloses an improved DRAM-based memory architecture, for use in conjunction with a network processor or other processing device, which can provide the storage capacity and low power consumption advantages of DRAMs while also providing the advantage of SRAMs in terms of avoiding the problems associated with the above-described bank conflict penalty.
In performing packet processing operations such as routing or switching, the network processor typically must examine at least a portion of the beginning or head of each packet. The amount of each packet that must be examined is dependent upon its associated network communication protocols, enabled options, and other similar factors. The sophistication or complexity of the router or switch can also influence the amount of each packet that will need examination.
Many conventional routers and switches are configured to store, for a given packet being processed, substantially the entire packet, until that packet is finally transmitted to its destination or dropped. The packet is usually stored in a router or switch memory external to the associated network processor. The amount of time the given packet may be kept in external memory is influenced by the basic processing time of the router or switch, the quality of service applied to the packet, the particular protocol layers to be analyzed, and the congestion of the port or other communication channel to which the packet is directed.
High-speed routers and switches will typically store in on-chip memory within the network processor some portion of a given packet being processed by that network processor. This greatly enhances the performance of the router or switch by not requiring it to access the larger external memory holding the entire packet, in that the external memory is slower and more band-limited than the on-chip memory. However, in conventional practice, the worst-case packet portion that may need to be analyzed in a given router or switch application usually dictates the size of every packet portion kept in on-chip memory, even though the worst-case packet portion may be associated with only certain rarely-occurring packets. This significantly increases the required size of the on-chip memory, and thus the cost and complexity of the network processor.
U.S. Patent Application Publication No. 2003/0112801, entitled “Processor with Reduced Memory Requirements for High-Speed Routing and Switching of Packets,” commonly assigned herewith and incorporated by reference herein, discloses improved techniques for determining particular portions of packets to be stored in particular memories associated with a network processor or other type of processor, so as to reduce the memory requirements of the device.
Despite the above-noted advancements, a need remains for further improvements in network processors. More particularly, conventional processors are inflexible in terms of the manner in which they translate logical addresses to physical addresses, and therefore may not provide optimal memory bandwidth and memory usage.
In one conventional approach, a given physical memory is not shared by multiple clients, but is instead assigned in its entirety to a single client. A “client” in this context refers to a network processor logic entity or other hardware or software entity that requires access to physical memory. The physical memory may comprise, for example, a multi-bank memory comprising a plurality of banks, with each bank having a plurality of pages. A read or write request issued by the client specifies a logical address. A rigid address translation is performed where the logical address presented by the client is mapped to a physical address for the multi-bank memory. The physical address includes a bank address portion and a page address portion. The mapping of logical address to physical address uses bits in the logical address to determine the bank address of the multi-bank memory. The page address portion of the physical address is given by the logical address less the bits that were utilized for the bank address.
Other conventional approaches allow physical memory to be shared by multiple clients, typically using either vertical striping or horizontal striping. Vertical striping refers to an arrangement in which each client is assigned one or more banks of a multi-bank memory, while in horizontal striping each client is assigned a range of pages across all banks of a multi-bank memory. However, these approaches also involve performing a rigid translation of logical address to physical address.
The rigid address translation requirements of the conventional approaches described above can make the processor inefficient in certain applications. For example, the address translation is not programmable on a client-by-client basis, nor does it provide the memory controller with information which could be used to optimize memory bandwidth.
Accordingly, improved address translation techniques are needed which overcome the above-noted deficiencies.